1. Field of the Invention
The present invention relates to a semiconductor substrate having a partially formed SOI region. In particular, the present invention relates to a semiconductor substrate having a single crystal silicon layer formed by epitaxial growth. In addition, the present invention relates to a semiconductor device including the semiconductor substrate, and methods of manufacturing these semiconductor substrate and device.
2. Description of the Related Art
Recently, demands for semiconductor devices embedding high performance logic circuit and DRAM are greatly growing. In order to meet the demands, the following technique is much required. According to the technique, a DRAM is embedded in a high performance logic circuit using a semiconductor substrate (SOI substrate) having an SOI (Silicon On Insulator) structure. In particular, a SOI-MOSFET having MOSFET formed on the SOI substrate is hopeful as the high performance logic circuit.
However, even if gate voltage is (OFF state) due to a so-called substrate floating effect, parasitic MOSFET and bipolar currents flow, as the leakage current between the source and drain depend on the potential difference between source and drain. Such a phenomenon is a factor of causing the reduction of deterioration in memory cell transistors of DRAMs, that is, portions requiring strict specifications against leakage current. In addition, the threshold value of pair transistors included in a DRAM sense amplifier circuit shifts due to the substrate floating effect; and due to this, the sense margin lowers. Due to this, it is difficult to form a DRAM having the same MOSFET structure as a high performance logic circuit on a general SOI substrate.
The use of a so-called partial SOI substrate having a partial SOI structure has been tried. In a partial SOI structure, a silicon layer is composed of two regions, that is, an SOI region and a non-SOI region. For example, the transistor is formed in the non-SOI region (bulk region), and thereby, it is possible to prevent the substrate floating effect. As described above, the partial SOI substrate is effective in circuits requiring both an SOI region and bulk region, such as DRAM embedded LOGIC and embedded DRAM (eDRAM).
The following method of manufacturing a partial SOI substrate is employed. According to the method, a SOI layer on the SOI substrate and a BOX (Buried Oxide) layer are selectively removed by etching to form a region, and this formed region is again covered with silicon. In addition, the following method is employed. According to the method, oxygen is partially implanted in the silicon substrate, and an isolation oxide film is formed only in the implanted region. However, according to the methods described above, if the bulk region adjacent to the SOI region is contaminated with heavy metals, the gettering ability of the SOI region is not sufficient. For this reason, it is difficult to stably obtain a stable yield. A so-called bonding method is employed other than these methods described above. According to the bonding method, an oxide film is formed on part of the silicon substrate, and silicon is deposited on the oxide film. Thereafter, the formed silicon substrate and another silicon substrate are bonded together so that a partial SOI structure can be made. The bonding method will be briefly described below with reference to FIG. 7A to FIG. 7F, FIG. 8A and FIG. 8B.
As illustrated in FIG. 7A, a multi-layer comprising a non-single crystal silicon film 102, single crystal silicon film 103 and silicon oxide film (SiO2 film) 104 is formed on one main surface of a silicon substrate 101. As shown in FIG. 7B, the SiO2 film 104 is partially removed so that the surface of the single crystal silicon film 103 can be partially exposed. As seen from FIG. 7C, a silicon film 105 is deposited on the single crystal silicon film 103 and the SiO2 film 104 by epitaxial growth. In this case, the silicon film 105 is formed while being divided into two kinds of layer, due to the difference of the material quality of the front end (seed layer). Most of the silicon film 105a on the single crystal silicon film 103 is formed as a single crystal silicon film (layer) 105a. On the contrary, a silicon film 105b on the SiO2 film 104 is formed as a polycrystalline silicon film (layer) 105b. The single crystal silicon film 105a is deposited on the single crystal silicon film 103 while being integrated with the single crystal silicon film 103.
As shown in FIG. 7D, the surface of the single crystal silicon film 105a and the polycrystalline silicon film 105b is planarized. Thereafter, another silicon substrate 106 used as a support substrate (base wafer) is bonded onto the surface of the films 105a and 105b. The silicon substrate 106 is formed of single crystal silicon, and integrated with the single crystal silicon film 105a. As illustrated in FIG. 7E, the silicon substrate 101 is cut off in the non-single crystal silicon film 102. Thereafter, an active layer side silicon film (single crystal silicon film 103) formed with semiconductor devices (not shown) is made thin. As seen from FIG. 7F, the non-single crystal silicon film 102 is polished and removed. Thereafter, predetermined surface processing, such as planarization, is subjected to the surface of the single crystal silicon film 103. The process described above is carried out, and thereby, a partial SOI substrate 107 having a partial SOI structure is manufactured.
In the partial SOI substrate 107, the polycrystalline silicon film (non-single crystal silicon film) 105b adjacent to the single crystal silicon film 105a functions as a gettering site. Thus, a high yield can be stably obtained. However, the polycrystalline silicon film 105b has a growth rate higher than the single crystal silicon film 105a. For this reason, the interface between the single crystal silicon film 105a and the polycrystalline silicon film 105b is inclined to the single crystal silicon film 105a side, as shown in FIG. 7C. As a result, as seen from FIG. 8A, in the non-SOI region (bulk region), an element formable region having a sufficient film thickness (depth) for forming buried semiconductor elements decreases. In addition, the decreased amount increases while the required thickness becomes gradually thick, as seen from FIG. 8B. For example, the element formable region is formed thicker in order to form devices such as memory trench cells extending in the depth direction. In this case, there is a high possibility that the element crosses the interface (epi/sub surface) between the single crystal silicon film 105a and the polycrystalline silicon film 105b. 
As described above, it is difficult to form the semiconductor elements such as DRAM on the general SOI substrate having the possibility of causing substrate floating effect. In addition, the method of forming the partial SOI structure having the following SOI region using epitaxial growth is not still established. The SOI region has gettering ability sufficient to adjacent bulk region, and has no possibility of reducing the bulk region (element formable region).